Referring to FIG. 1, an electrical coupling network between a static random access memory 20a (hereinafter xe2x80x9cSRAM 20axe2x80x9d) and a static random access memory 20b (hereinafter xe2x80x9cSRAM 20bxe2x80x9d) is shown. SRAM 20a and SRAM 20b are identical memory devices. Specifically, both SRAM 20a and SRAM 20b have an identical pin arrangement including seven (7) rows and seventeen (17) columns of pins. The first column of pins are shown in FIG. 1. In the first column of pins, SRAM 20a includes two (2) output power supply pins 21a and 27a, and SRAM 20b includes two (2) output power supply pins 21b and 27b. Also in the first column of pins, SRAM 20a includes four (4) synchronous address input pins 22a, 23a, 25a, and 26a, and SRAM 20b includes four (4) synchronous address input pins 22b, 23b, 25b, and 26b. Pin 24a of SRAM 20a and pin 24b of SRAM 20b are not utilized.
In support of four (4) cache configurations, SRAM 20a is mounted to a front side of a processor card 10, and SRAM 20b is mounted to a rear side of processor card 10. SRAM 20a and SRAM 20b are positioned with an alignment of pin 21a and pin 27b, an alignment of pin 22a and pin 26b, an alignment of pin 23a and pin 25b, an alignment of pin 24a and pin 24b, an alignment of pin 25a and pin 23b, an alignment of pin 26a and pin 22b, and an alignment of pin 27a and pin 21b. 
Pin 22a and pin 22b are functionally equivalent and electrically coupled via a conductor 28a within processor card 10 to concurrently receive a first address bit signal from a microprocessor. Pin 23a and pin 23b are functionally equivalent and electrically coupled via a conductor 28b within processor card 10 to concurrently receive a second address bit signal from the microprocessor. Pin 25a and pin 25b are functionally equivalent and electrically coupled via a conductor 28c within processor card 10 to concurrently receive a third address bit signal from the microprocessor. Pin 26a and pin 26b are functionally equivalent and electrically coupled via a conductor 28d within processor card 10 to concurrently receive a fourth address bit signal from the microprocessor. The four (4) address bits signal are selectively provided by the microprocessor as a function of a selected cache configuration.
A drawback associated with the aforementioned electrical couplings as shown is the length of conductors 28a-28d tends to establish a maximum frequency at which the microprocessor can effectively and efficiently control SRAM 20a and SRAM 20b, and the established maximum frequency can be significantly lower than a desired operating frequency of the microprocessor. The computer industry is therefore continually striving to improve upon the electrical coupling between the synchronous address input pins of SRAM 20a and SRAM 20b whereby a maximum frequency at which a microprocessor can effectively and efficiently control SRAM 20a and SRAM 20b matches a desired operating frequency of the microprocessor. The computer industry is also continually striving to improve upon the electrical communication of a selected cache configuration from a microprocessor to the synchronous address input pins of SRAM 20a and SRAM 20b. 
The present invention generally relates to computer hardware mounted upon a processor card, and in particular to an electrical coupling between memory components for supporting multiple cache configurations and an electrical communication from a microprocessor to the memory components for selecting one of the supported multiple cache configurations.
One form of the present invention is a processor card having a first memory device and a second memory device mounted thereon. The first memory device includes a first address pin and a second address pin. The second memory device includes a third address pin and a fourth address pin. The first address pin of the first memory device and the third address pin of the second memory device are functionally equivalent address pins. The second address pin of the first memory device and the fourth address pin are functionally equivalent address pins. The first address pin of the first memory device and the fourth address pin of the second memory device are electrically coupled to thereby concurrently receive a first address bit signal. The second address pin of the first memory device and the third address pin of the second memory device are electrically coupled to thereby concurrently receive a second address bit signal.
Another form of the present invention is a system including a first memory device, a second memory device, and a microprocessor. The first memory device includes a first address pin and a second address pin. The second memory device includes a third address pin and a fourth address pin. The first address pin of the first memory device and the third address pin of the second memory device are functionally equivalent address pins. The second address pin of the first memory device and the fourth address pin are functionally equivalent address pins. The microprocessor is operable to concurrently provide a first address bit signal to first address pin of the first memory device and the fourth address pin of the second memory device. The microprocessor is further operable to concurrently provide a first address bit signal to second address pin of the first memory device and the third address pin of the second memory device.
The foregoing and other features and advantages of the invention will become further apparent from the following detailed description of the presently preferred embodiments, read in conjunction with the accompanying drawings. The detailed description and drawings are merely illustrative of the invention rather than limiting, the scope of the invention being defined by the appended claims and equivalents thereof.